Anomalies LLC — Stochastic Anomaly Detection

Our Approach

Stochastic Anomaly Theory

A fundamentally different way to find anomalies in sensor data — no training sets, no labeled data, no retraining cycles.

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Ab Initio Detection

Works from first principles using physics-based statistical signatures. No pre-collected training datasets required — effective from day one against novel targets.

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Multi-Probe Analysis

K=6 independent statistical probes analyze every sensor tile simultaneously. Redundant, orthogonal detection channels minimize false negatives and false positives.

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Dual-Filter Architecture

Anomaly detection and classification in a single pass. The engine doesn't just find anomalies — it categorizes and prioritizes them in real-time.

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Multi-Sensor Fusion

Native ingestion of EO/IR, 4D AESA radar (with micro-Doppler), passive RF, acoustic, ADS-B, and Remote ID. Correlated detections across modalities reduce ambiguity and reject substrate-specific false positives.

Performance

Proven Capabilities

Measured on Anti-UAV300 and on physics-aligned synthetic substrates with operationally realistic clutter.

<2 ms

Per-frame Latency (FPGA)

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Xilinx Artix-7, 28 nm — 200 MHz clock
80 tiles processed in parallel per 640×512 frame
One tile dispatched every ∼5.1 μs
5-stage fixed pipeline — no data-dependent branching
Q16.16 fixed-point arithmetic — no FPU required
Deterministic: worst-case = best-case = typical-case
ASIC roadmap: 400 MHz → <0.5 ms at <100 mW

<500 mW

Power Envelope

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FPGA (Artix-7): ∼350 mW dynamic + static
ASIC (28 nm CMOS): <80 mW dynamic + <20 mW leakage
No GPU — no neural-network accelerator
Die area: <1 mm² at 28 nm node
Unit cost: <\$3 at 100K volume; ∼\$12 at 10K
ITAR-free silicon options available

Labelled Samples Required

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Background-only calibration — target-free prefix
<500 bytes payload over SPI at power-on
Operator A derived analytically from K-stability constraint
No gradient descent — no data collection pipeline
Adaptive β* recalibrates per substrate automatically
Operational against novel targets from day one

+72%

F1 over Best Classical Detector

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Anti-UAV300 real RGBT: F1 = 0.503 vs 0.289 unregistered baseline
Trimodal synthetic (EO+IR+Radar): F1 = 0.805, R = 0.999
Foliage clutter: F1 = 0.882 — zero missed detections
Sea-wave clutter: F1 = 0.775 with +39% precision vs additive
4-sensor fusion: EO, IR, 4D AESA radar, passive RF
Temporal gate reduces FP by 37% with <8% recall loss

Substrate-Adaptive ▼

Same engine, no retraining. F1 = 0.88 on foliage clutter (zero misses). F1 = 0.78 on sea-wave clutter with +39% precision uplift vs. additive baseline.

Clear sky (reference): F1 = 0.844, R = 1.000, P = 0.730
Foliage wind clutter: F1 = 0.882, R = 1.000 — leaf-flutter Doppler rejected
Sea-wave clutter: F1 = 0.775, R = 0.897 — MIN consensus fusion
Dynamic β* auto-recalibrates per substrate at power-on
K-stability theory ensures graceful degradation under clutter
Mission-reconfigurable in <500 bytes over SPI

Silicon-Native ▼

FPGA prototype at <500 mW, 200 MHz, 30 fps on 640×512 dual sensors. ASIC projection: <100 mW, <1 mm² die at 28 nm. No GPU, no neural-network accelerator.

Artix-7: LUTs 38%, DSP48E1 53%, BRAM 84% — timing closed at 200 MHz
~\$12/unit at 10K volume; no NRE for FPGA deployment
ASIC (28 nm): ~200K gates, <1 mm², 400 MHz, <100 mW total
ASIC unit cost: <\$3 at 100K volume; NRE ~\$500K–\$1M tape-out
Zero neural-network weights — operator A fits in <1 KB registers
Pure RTL — no soft-core CPU in the critical path

Certification-Ready ▼

Deterministic fixed-point datapath. Pure RTL, no soft-core in the critical path. DO-254 DAL-C posture; MIL-STD-810H / 461G qualification at integration. ITAR-free silicon options available.

DO-254 DAL-C: 100% RTL coverage, tool qualification — 3–6 months
MIL-STD-810H environmental / 461G EMC — at hardware integration
MIL-STD-882E: advisory cue only — no autonomous kinetic action
NIST SP 800-53: AES-128 SPI bus, on-die zeroisation <1 μs
CMMC 2.0 Level 2–3: formal threat model + SCRM plan (~2–4 weeks)
ITAR-free: PolarFire FPGA + GlobalFoundries 28 nm U.S. trusted foundry

System Design

Five-Stage Silicon Pipeline

Detection theory reduced to its algebraic minimum, expressed in silicon. Fixed datapath, deterministic latency, no external memory.

Tile Slicer

DMA ingestion from EO, IR, radar, RF, and ADS-B streams. Pixel-stream tiling.

Probe Extract

Six statistical probes per channel computed in a single pixel-stream pass.

Bilinear Score

K-stable operator. Three clocks per tile. Multi-sensor fusion in one bilinear form.

Temporal Gate

Per-tile temporal covariance with substrate-adaptive purification. Clutter rejection.

Decision

Threshold, blob merge, coordinate output. SPI / UART / MIL-STD-1553-ready.

Detect the unknown.Fuse every sensor.